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<CENTER><A HREF="../home.htm">Home</A> <A HREF="vga.htm#register">Back</A>&nbsp;
<HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
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<CENTER>Sequencer Registers&nbsp;
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<P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The Sequencer Registers are
accessed via a pair of registers, the Sequencer Address Register and the
Sequencer Data Register. See the <A HREF="vgareg.htm">Accessing the VGA
Registers</A> section for more detals. The Address Register is located
at port 3C4h and the Data Register is located at port 3C5h.
<UL>
<LI>
Index 00h -- <I>Reset Register</I></LI>

<LI>
Index 01h -- <I>Clocking Mode Register</I></LI>

<LI>
Index 02h -- <I>Map Mask Register</I></LI>

<LI>
Index 03h -- Character Map Select Register</LI>

<LI>
Index 04h -- <I>Sequencer Memory Mode Register</I></LI>
</UL>
&nbsp;
<TABLE BORDER WIDTH="600" CELLPADING="2" >
<CAPTION ALIGN=TOP><A NAME="00"></A><B>Reset Register (Index 00h)</B></CAPTION>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75">7</TD>

<TD WIDTH="75">6</TD>

<TD WIDTH="75">5</TD>

<TD WIDTH="75">4</TD>

<TD WIDTH="75">3</TD>

<TD WIDTH="75">2</TD>

<TD WIDTH="75">1</TD>

<TD WIDTH="75">0</TD>
</TR>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75">SR</TD>

<TD WIDTH="75">AR</TD>
</TR>
</TABLE>
&nbsp;
<UL><B>SR -- Sychnronous Reset</B>
<BR>"<I>When set to 0, this bit commands the sequencer to synchronously
clear and halt. Bits 1 and 0 must be 1 to allow the sequencer to operate.
To prevent the loss of data, bit 1 must be set to 0 during the active display
interval before changing the clock selection. The clock is changed through
the Clocking Mode register or the Miscellaneous Output register.</I>"
<BR><B>AR -- Asynchronous Reset</B>
<BR>"<I>When set to 0, this bit commands the sequencer to asynchronously
clear and halt. Resetting the sequencer with this bit can cause loss of
video data</I>"</UL>
&nbsp;
<TABLE BORDER WIDTH="600" CELLPADING="2" >
<CAPTION ALIGN=TOP><A NAME="01"></A><B>Clocking Mode Register (Index 01h)</B></CAPTION>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75">7</TD>

<TD WIDTH="75">6</TD>

<TD WIDTH="75">5</TD>

<TD WIDTH="75">4</TD>

<TD WIDTH="75">3</TD>

<TD WIDTH="75">2</TD>

<TD WIDTH="75">1</TD>

<TD WIDTH="75">0</TD>
</TR>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75">SD</TD>

<TD WIDTH="75">S4</TD>

<TD WIDTH="75">DCR</TD>

<TD WIDTH="75">SLR</TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75">9/8DM</TD>
</TR>
</TABLE>
&nbsp;
<UL><B>SD -- Screen Disable</B>
<BR>"<I>When set to 1, this bit turns off the display and assigns maximum
memory bandwidth to the system. Although the display is blanked, the synchronization
pulses are maintained. This bit can be used for rapid full-screen updates.</I>"
<BR><B>S4 -- Shift Four Enable</B>
<BR>"<I>When the Shift 4 field and the Shift Load Field are set to 0, the
video serializers are loaded every character clock. When the Shift 4 field
is set to 1, the video serializers are loaded every forth character clock,
which is useful when 32 bits are fetched per cycle and chained together
in the shift registers.</I>"
<BR><B>DCR -- Dot Clock Rate</B>
<BR>"<I>When set to 0, this bit selects the normal dot clocks derived from
the sequencer master clock input. When this bit is set to 1, the master
clock will be divided by 2 to generate the dot clock. All other timings
are affected because they are derived from the dot clock. The dot clock
divided by 2 is used for 320 and 360 horizontal PEL modes.</I>"
<BR><B>SLR -- Shift/Load Rate</B>
<BR>"<I>When this bit and bit 4 are set to 0, the video serializers are
loaded every character clock. When this bit is set to 1, the video serializers
are loaded every other character clock, which is useful when 16 bits are
fetched per cycle and chained together in the shift registers. The Type
2 video behaves as if this bit is set to 0; therefore, programs should
set it to 0.</I>"
<LI>
<B>9/8DM -- 9/8 Dot Mode</B></LI>

<BR>This field is used to select whether a character is 8 or 9 dots wide.
This can be used to select between 720 and 640 pixel modes (or 360 and
320) and also is used to provide 9 bit wide character fonts in text mode.
The possible values for this field are:
<UL>
<LI>
0 - Selects 9 dots per character.</LI>

<LI>
1 - Selects 8 dots per character.</LI>
</UL>
</UL>
&nbsp;
<TABLE BORDER WIDTH="600" CELLPADING="2" >
<CAPTION ALIGN=TOP><A NAME="02"></A><B>Map Mask Register (Index 02h)</B></CAPTION>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75">7</TD>

<TD WIDTH="75">6</TD>

<TD WIDTH="75">5</TD>

<TD WIDTH="75">4</TD>

<TD WIDTH="75">3</TD>

<TD WIDTH="75">2</TD>

<TD WIDTH="75">1</TD>

<TD WIDTH="75">0</TD>
</TR>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD COLSPAN="4" WIDTH="300">Memory Plane Write Enable</TD>
</TR>
</TABLE>
&nbsp;
<UL>
<LI>
<B>Memory Plane Write Enable</B></LI>

<BR>Bits 3-0 of this field correspond to planes 3-0 of the VGA display
memory. If a bit is set, then write operations will modify the respective
plane of display memory. If a bit is not set then write operations will
not affect the respective plane of display memory.</UL>
&nbsp;
<TABLE BORDER WIDTH="600" CELLPADING="2" >
<CAPTION ALIGN=TOP><A NAME="03"></A><B>Character Map Select Register (Index
03h)</B></CAPTION>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75">7</TD>

<TD WIDTH="75">6</TD>

<TD WIDTH="75">5</TD>

<TD WIDTH="75">4</TD>

<TD WIDTH="75">3</TD>

<TD WIDTH="75">2</TD>

<TD WIDTH="75">1</TD>

<TD WIDTH="75">0</TD>
</TR>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75">CSAS2</TD>

<TD WIDTH="75">CSBS2</TD>

<TD COLSPAN="2" WIDTH="150">Character Set A Select</TD>

<TD COLSPAN="2" WIDTH="150">Character Set B Select</TD>
</TR>
</TABLE>
&nbsp;
<UL>
<LI>
<B>CSAS2 -- Bit 2 of Character Set A Select</B></LI>

<BR>This is bit 2 of the Character Set A Select field. See <A HREF="#03">Character
Set A Select</A> below.
<LI>
<B>CSBS2 -- Bit 2 of Character Set B Select</B></LI>

<BR>This is bit 2 of the Character Set B field. See <A HREF="#03">Character
Set B Select</A> below.
<LI>
<B>Character Set A Select</B></LI>

<BR>This field is used to select the font that is used in text mode when
bit 3 of the attribute byte for a character is set to 1. Note that this
field is not contiguous in order to provide EGA compatibility. The font
selected resides in plane 2 of display memory at the address specified
by this field, as follows:
<UL>
<LI>
000b -- Select font residing at 0000h - 1FFFh</LI>
</UL>

<UL>
<LI>
001b -- Select font residing at 4000h - 5FFFh</LI>

<LI>
010b -- Select font residing at 8000h - 9FFFh</LI>

<LI>
011b -- Select font residing at C000h - DFFFh</LI>

<LI>
100b -- Select font residing at 2000h - 3FFFh</LI>

<LI>
101b -- Select font residing at 6000h - 7FFFh</LI>

<LI>
110b -- Select font residing at A000h - BFFFh</LI>

<LI>
111b -- Select font residing at E000h - FFFFh</LI>
</UL>

<LI>
<B>Character Set B Select</B></LI>

<BR>This field is used to select the font that is used in text mode when
bit 3 of the attribute byte for a character is set to 0. Note that this
field is not contiguous in order to provide EGA compatibility. The font
selected resides in plane 2 of display memory at the address specified
by this field, identical to the mapping used by <A HREF="#03">Character
Set A Select</A> above.</UL>
&nbsp;
<TABLE BORDER WIDTH="600" CELLPADING="2" >
<CAPTION ALIGN=TOP><A NAME="04"></A><B>Sequencer Memory Mode Register (Index
04h)</B></CAPTION>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75">7</TD>

<TD WIDTH="75">6</TD>

<TD WIDTH="75">5</TD>

<TD WIDTH="75">4</TD>

<TD WIDTH="75">3</TD>

<TD WIDTH="75">2</TD>

<TD WIDTH="75">1</TD>

<TD WIDTH="75">0</TD>
</TR>

<TR ALIGN=CENTER VALIGN=CENTER>
<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75"></TD>

<TD WIDTH="75">Chain 4</TD>

<TD WIDTH="75">O/E Dis.</TD>

<TD WIDTH="75">Ext. Mem</TD>

<TD WIDTH="75"></TD>
</TR>
</TABLE>
&nbsp;
<UL><B>Chain 4 -- Chain 4 Enable</B>
<BR>"<I>This bit controls the map selected during system read operations.
When set to 0, this bit enables system addresses to sequentially access
data within a bit map by using the Map Mask register. When setto 1, this
bit causes the two low-order bits to select the map accessed as shown below.</I>
<BR><I>Address Bits</I>
<BR><I>&nbsp; A0 A1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Map Selected</I>
<BR><I>&nbsp;&nbsp; 0&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
0</I>
<BR><I>&nbsp;&nbsp; 0&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
1</I>
<BR><I>&nbsp;&nbsp; 1&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
2</I>
<BR><I>&nbsp;&nbsp; 1&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
3</I>"
<BR><B>O/E Dis. -- Odd/Even Host Memory Write Adressing Disable<BR>
</B>"<I>When this bit is set to 0, even system addresses access maps 0
and 2, while odd system addresses access maps 1 and 3. When this bit is
set to 1, system addresses sequentially access data within a bit map, and
the maps are accessed according to the value in the Map Mask register (index
0x02).</I>"
<BR><B>Ext. Mem -- Extended Memory<BR>
</B>"<I>When set to 1, this bit enables the video memory from 64KB to 256KB.
This bit must be set to 1 to enable the character map selection described
for the previous register.</I>"</UL>
Notice: All trademarks used or referred to on this page are the property
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<BR>All pages are Copyright &copy; 1997, 1998, J. D. Neal, except where
noted. Permission for utilization and distribution is subject to the terms
of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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